Chapter 252: ESP32-S2 Architecture and Differences

Chapter Objectives

By the end of this chapter, you will be able to:

• Describe the single-core Xtensa LX7 CPU architecture of the ESP32-S2.
• Explain the key architectural trade-offs compared to the original ESP32, most notably the single-core design and lack of Bluetooth.
• Detail the new peripherals introduced in the ESP32-S2, with a focus on its native USB On-The-Go (OTG) capabilities.
• Understand the enhanced security features and the updated ULP coprocessor architecture.
• Identify the target applications for the ESP32-S2, such as HMI devices and secure endpoints.
• Write and run code that utilizes ESP32-S2-specific features like the USB CDC console.

Introduction

After mastering the architecture of the original ESP32, we now turn our attention to its first major successor: the ESP32-S2. The S2 is not a direct replacement for the ESP32; rather, it’s a carefully tailored variant designed for a different set of applications. Espressif designed the S2 by making deliberate trade-offs: they removed the Bluetooth radio and one of the CPU cores, but in their place added native USB support, enhanced security features, and a suite of new peripherals ideal for human-machine interfaces (HMIs).

Understanding the ESP32-S2 is key to choosing the right chip for your project. If your application needs to act as a USB device, requires robust security, and can operate without Bluetooth or true parallel processing, the S2 presents a power-efficient and cost-effective solution. This chapter explores its unique architecture, highlights its strengths, and provides practical examples to get you started with its most important features.

Theory

The ESP32-S2 represents a significant architectural shift from the original ESP32, prioritizing security, low power, and USB connectivity.

1. CPU and Memory

• Single-Core Architecture: The most significant change is the move from a dual-core LX6 to a single-core Xtensa LX7 CPU. While it loses the parallel processing capability of its predecessor, the LX7 core is more powerful and efficient than the LX6, capable of running at up to 240 MHz. This single-core design simplifies programming models, as you no longer need to manage task affinity between two cores. All tasks, including the Wi-Fi stack and application code, share the same CPU resources, managed by FreeRTOS’s time-slicing scheduler.
• Memory: The ESP32-S2 features 320 KB of on-chip SRAM and 128 KB of ROM. This is a reduction from the 520 KB of SRAM in the original ESP32, reinforcing its positioning for more focused applications rather than general-purpose, memory-heavy tasks. The memory is still partitioned into IRAM and DRAM for efficient instruction and data access.
• ULP Coprocessor Update: The Ultra Low-Power (ULP) coprocessor also received an upgrade. Instead of the custom Finite State Machine (FSM) architecture of the ESP32, the ESP32-S2’s ULP is based on a RISC-V core. This is a major improvement for developers, as it allows ULP programs to be written in standard C, compiled with a familiar toolchain, and debugged more easily.

%%{init: {'theme': 'base', 'themeVariables': {'fontFamily': 'Open Sans, sans-serif'}}}%%
graph TD
    subgraph "ESP32 (Original)"
        direction TB
        A[Developer] --> B{Custom<br>FSM Assembly};
        B --> C[ULP Program];
    end

    subgraph "ESP32-S2 (New)"
        direction LR
        D[Developer] --> E{"Standard C Code<br><i>(e.g., main_ulp.c)</i>"};
        E --> F[RISC-V<br>GCC Toolchain];
        F --> G[ULP Program];
    end

    subgraph Advantages
        Adv1(<b>Easier to Program</b>)
        Adv2(<b>Familiar Tooling</b>)
        Adv3(<b>More Powerful & Flexible</b>)
    end
    
    G -.-> Adv1;
    G -.-> Adv2;
    G -.-> Adv3;


    %% Styling %%
    classDef old_ulp fill:#FEE2E2,stroke:#DC2626,stroke-width:1px,color:#991B1B;
    classDef new_ulp fill:#DBEAFE,stroke:#2563EB,stroke-width:1px,color:#1E40AF;
    classDef dev fill:#FEF3C7,stroke:#D97706,stroke-width:1px,color:#92400E;
    classDef advantage fill:#D1FAE5,stroke:#059669,stroke-width:2px,color:#065F46;

    class A,D dev;
    class B,C old_ulp;
    class E,F,G new_ulp;
    class Adv1,Adv2,Adv3 advantage;

2. Connectivity: Wi-Fi Yes, Bluetooth No

• Wi-Fi: The ESP32-S2 includes the same robust Wi-Fi 4 (802.11 b/g/n) radio found in the original.
• No Bluetooth: In a key strategic decision, the ESP32-S2 completely removes the Bluetooth hardware. This reduces the cost, power consumption, and complexity of the chip. If your application requires any form of Bluetooth (Classic or LE), the ESP32-S2 is not a suitable choice.

3. The Headline Feature: USB On-The-Go (OTG)

The most compelling reason to choose an ESP32-S2 is its full-speed USB 2.0 On-The-Go (OTG) interface. Unlike the original ESP32, which relied on an external USB-to-UART bridge chip for communication and programming, the S2 has this capability built directly into the silicon.

• Device Mode: The S2 can act as a USB device, emulating various device classes. The most common is CDC (Communications Device Class), which allows it to appear as a standard serial port to a host computer for logging and communication. Other classes like MSC (Mass Storage Class) and HID (Human Interface Device) are also possible.
• Host Mode: The S2 can also act as a USB host, allowing it to connect to and control other USB devices like keyboards, mice, or flash drives.

Analogy: USB OTG Think of the original ESP32’s USB port as a landline telephone—it can only talk to the exchange (the UART bridge chip). The ESP32-S2’s USB OTG port is like a smartphone—it can make calls (act as a host) and receive them (act as a device).

%%{init: {'theme': 'base', 'themeVariables': {'fontFamily': 'Open Sans, sans-serif'}}}%%
graph TB
    subgraph "Original ESP32"
        direction TB
        A(<b>ESP32</b>) -- UART --> B(USB-to-Serial<br>Bridge Chip);
        B -- USB --> C([PC]);
        subgraph "Fixed Role"
           direction LR
           D{Can only talk<br>via the bridge chip}
        end
        A-.->D
    end
    
    subgraph "ESP32-S2"
        direction TB
        E(<b>ESP32-S2</b>)
        subgraph "Flexible Roles (OTG)"
            direction LR
            F{"Can act as a<br><b>Device</b><br><i>(e.g., Serial Port, Keyboard)</i>"}
            G{"Can act as a<br><b>Host</b><br><i>(Control a Mouse, Flash Drive)</i>"}
        end
        E -- Native USB --> H([PC]);
        E -- Native USB --> I([USB Keyboard]);
        E -.-> F
        E -.-> G
    end

    %% Styling %%
    classDef original fill:#FEE2E2,stroke:#DC2626,stroke-width:1px,color:#991B1B;
    classDef s2 fill:#D1FAE5,stroke:#059669,stroke-width:1px,color:#065F46;
    classDef device fill:#DBEAFE,stroke:#2563EB,stroke-width:1px,color:#1E40AF;
    classDef role fill:#FEF3C7,stroke:#D97706,stroke-width:1px,color:#92400E;

    class A,B original;
    class E s2;
    class C,H,I device;
    class D,F,G role;

4. New Peripherals and Enhanced Security

The S2 was built for a new generation of secure, interactive devices.

• HMI Peripherals: It introduces hardware support for LCD displays (parallel I/O) and DVP cameras, making it ideal for products with small screens or basic computer vision capabilities.
• Enhanced Security:
  • Secure Boot: The Secure Boot process is strengthened.
  • Flash Encryption: It uses the improved AES-XTS algorithm for encrypting external flash memory.
  • Digital Signature (DS) Peripheral: This is a hardware accelerator that can generate digital signatures using a private key stored in secure eFuses. This allows a device to prove its identity to a remote server without ever exposing its private key to software, which is a cornerstone of modern IoT security.
  • World Controller: A new peripheral that allows for the creation of two isolated execution environments (trusted and non-trusted), a feature useful for advanced security applications.

Practical Examples

Let’s explore the ESP32-S2’s flagship feature: the USB serial console.

Example 1: Native USB “Hello World”

This example configures the ESP32-S2 to output log messages over its native USB interface, which will appear as a new serial port on your computer.

1. Configure the Project:

1. Create a new project in VS Code using an ESP32-S2 target.
2. Open the menuconfig (Ctrl+Shift+P -> “ESP-IDF: SDK Configuration editor”).
3. Navigate to Component config -> ESP System Settings.
4. Ensure Channel for console output is set to USB Serial/JTAG Controller.
5. Save the configuration and exit.

2. Code: The beautiful part is that for basic logging, no code changes are needed! The standard ESP_LOGI functions are automatically routed to the configured console. Your main.c can be as simple as this:

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_log.h"

static const char *TAG = "USB_TEST";

void app_main(void)
{
    ESP_LOGI(TAG, "Hello from the ESP32-S2 Native USB!");

    for (int i = 10; i >= 0; i--) {
        ESP_LOGI(TAG, "Restarting in %d seconds...", i);
        vTaskDelay(pdMS_TO_TICKS(1000));
    }
    
    ESP_LOGI(TAG, "Restarting now.");
    esp_restart();
}

3. Build and Flash:

1. Connect your ESP32-S2 board. It must be put into bootloader mode for the initial flash. This is typically done by holding a “BOOT” button, pressing and releasing the “RESET” button, and then releasing “BOOT”.
2. Use the standard “ESP-IDF: Build, Flash and Monitor” command. VS Code will use the board’s physical UART for flashing.

4. Observe: After flashing, the device will restart. Your computer should detect a new serial port.

1. Open the VS Code command palette (Ctrl+Shift+P).
2. Select “ESP-IDF: Monitor Device”. If prompted, choose the new serial port (often named differently, e.g., /dev/ttyACM0 on Linux or a higher COM port on Windows) associated with the USB JTAG/Serial Controller, not the physical UART port used for flashing.
3. You will see the “Hello World” and countdown messages printed directly from the native USB interface.

Variant Notes

The ESP32-S2 fits into a specific niche between the original ESP32 and the more powerful ESP32-S3.

Common Mistakes & Troubleshooting Tips

Exercises

1. USB HID Keyboard: Elevate the practical example by turning the ESP32-S2 into a simple USB keyboard. Use the ESP-IDF USB HID driver examples as a reference. Configure the device so that when you press a button connected to a GPIO, it sends the keystrokes for the message “Hello from my ESP32-S2!” to the connected computer.
2. Deep Sleep with GPIO Wakeup: The ESP32-S2 is designed for low-power applications. Write a program that configures a GPIO pin as a wakeup source. The device should enter deep sleep, consuming minimal power. When a button connected to the wakeup pin is pressed, the device should wake up, print a message over the USB console, and go back to sleep. Use an ammeter or a power profiler to observe the current draw in deep sleep.

Summary

• The ESP32-S2 is a specialized variant featuring a single, more powerful Xtensa LX7 core.
• It strategically removes Bluetooth to reduce cost and power but keeps Wi-Fi 4.
• Its flagship feature is a native USB OTG controller, allowing it to act as a USB device (like a serial port or keyboard) or a host.
• The ULP coprocessor is upgraded to a more user-friendly RISC-V core.
• It introduces new peripherals for HMI applications (LCD, Camera) and enhanced security features like the Digital Signature peripheral.
• The ESP32-S2 is the ideal choice for secure, low-power IoT endpoints that require USB connectivity but not Bluetooth.

Further Reading

• ESP32-S2 Technical Reference Manual: The definitive guide to the S2’s hardware architecture.
  • ESP32-S2 Technical Reference Manual (PDF)
• ESP-IDF Programming Guide – USB Serial/JTAG Controller Console: Official documentation for the feature shown in the practical example.
  • USB Serial/JTAG Console
• ESP-IDF Programming Guide – USB Host and Device Drivers: A starting point for building more complex USB applications.
  • USB Host Stack